The present invention relates to an arithmetic circuit provided in a microprocessor or the like.
When, for example, an arithmetic circuit having a 8-bit width is used to add data A and B each having a 16-bit width, thereby obtaining data C corresponding to the result of their addition, the process of adding such data has heretofore been carried out according to the following procedures.
(Procedure 1) Lower 8 bits of data A and B are inputted to the arithmetic circuit to execute an add instruction. Thus, lower 8 bits of data C are outputted from the arithmetic circuit. If a carry is produced in it, then a C flag is set to “1”. If the value of the lower 8 bits of the data C is 0, then a Z flag is set to “1”.
(Procedure 2) Upper 8 bits of the data A and B are inputted to the arithmetic circuit to execute an add instruction with a carry. Thus, upper 8 bits of data C are outputted from the arithmetic circuit. If a carry exists in it, then the C flag is set to “1”. If the value of the upper 8 bits of the data C is 0, then the value of the Z flag is set to “1”. If the value thereof is not 0, then the value of the Z flag is set to “0”.
As a result, the data C indicative of the result of addition of 17 bits is obtained inclusive of the carry from the lower 8 bits of the data C obtained in the procedure 1, and the upper 8 bits of the data C and the value of the C flag both obtained in the procedure 2.
The conventional arithmetic circuit, however, has the following problems.
The value of the Z flag, which has finally been set as a result of the procedure 2, indicates whether the value of the upper 8 bits of the data C is 0, but does not indicate whether the value of 16 bits of the data C corresponding to the result of addition is 0. Therefore, there was further a need to execute the following procedures with a view toward examining whether the result of addition is 0.
(Procedure 3) The value of the Z flag, which has been set in the procedure 2, is examined. If the value of the Z flag is found to be “0”, it is then determined that the result of addition is not 0. If the value of the Z flag is found to be “1”, then the following procedure 4 is executed.
(Procedure 4) Check is made as to whether the value of the lower 8 bits of the data C, which have been obtained in the procedure 1, is 0. Described specifically, 0 is added to the lower 8 bits of the data C. If the value of the Z flag, which is indicative of the result of addition, is “1”, then the value of 16 bits of the data C is judged to be 0.
In the conventional arithmetic circuit as described above, the value of the Z flag obtained in the final arithmetic operation does not correspond to the whole result of arithmetic operation where the arithmetic operation of numeral values each exceeding a bit width of the arithmetic circuit is carried out in a divided form. Therefore, a problem arises in that there is a need to execute add processing with a view toward obtaining the proper value of the Z flag, and the number of program-steps increases and a processing time becomes long.
Similarly, a problem arises in that when shift operations are effected on a plurality of bits, for example, the result of final shift processing is set to the C flag and left behind where one-bit shift processing is repeated plural times, and the whole result of shift arithmetic operation is not reflected on the C flag.